1. Field of the Invention
The present invention relates to an arbiter circuit that arbitrates a plurality of requests in a computer.
2. Description of the Related Art
Conventionally, read or write requests from a plurality of requesters, e.g., blocks processing or storing data, are arbitrated in a computer such that the requests are accepted, or a right to use the bus is granted, according to predetermined priority levels. For example, the arbitration priority levels are set such that the number of accepted requests is equalized as much as possible among the requesters.
An arbitration control circuit is known that performs arbitration depending on the number of bus acquisition requests from a plurality of devices connected to a bus. Such arbitration control circuit includes an arbitration counter that counts the number of bus acquisition requests output from each of the devices, a priority setting unit that sets priority levels for the devices in advance, and a priority determining unit that, when the devices connected to the bus issue bus acquisition requests, determines which device is given a right to use the bus based on the number counted by the arbitration counter and the priority levels set by the priority setting unit (for example, Japanese Patent Laid-Open Publication No. 2000-201161).
However, such arbitration based on the priority levels set in advance has a problem that it is not possible to freely change the priority levels, such that the number of requests accepted in one period is equalized as much as possible among the requesters, whereas a larger number of requests are accepted from a specific requester in another period. Although the controller disclosed in Japanese Patent Laid-Open Publication No. 2000-201161 is capable of control according to the number of bus acquisition requests, the arbitration priority levels cannot be changed from a requester side.